1. Field of Invention
The present invention relates to a flip-chip die and a flip-chip package substrate. More particularly, the present invention relates to a flip-chip die having a plurality of die pad rings and a flip-chip package substrate having a plurality of bump pad rings that corresponds to the flip-chip die.
2. Description of Related Art
Flip-chip (FC) bonding is a common type of packaging technique in a chip scale package (CSP). To form a flip-chip package, an array of die pads is formed on the active surface of a die. Thereafter, a bump is formed over each die pad. Finally, the bumps are attached to corresponding contacts on a carrier. In other words, the die is flipped over and bonded with the contacts on the carrier surface.
Due the various advantages such as an overall reduction in package area, an increase in package density and shortening of signal transmission paths, flip-chip bonding technique has been widely adopted in die packaging. This is especially true for high-pin-count package structures such as a ball grid array or a pin grid array. The idea of forming a high-pin-count package under a flip-chip configuration has lead to the manufacturing of flip-chip ball grid array (FCBGA) and flip-chip pin grid array (FCPGA) with each die containing a few hundred bonding pads.
In general, all flip-chip packages including the FCBGA and the FCPGA have a substrate. The substrate serves as a carrier for joining with a die. Each substrate comprises of a plurality of alternately stacked wiring layers and insulation layers. Each insulation layer has a plurality of through plugs for connecting neighboring wiring layers electrically. In addition, the upper surface of the substrate has a plurality of bump pads. Each bump pad connects to a corresponding bump on a die. The bottom surface of the substrate has a plurality of ball pads that connect electrically to the bump pads through internal circuits. A conductive structure such as a solder ball may be attached to each ball pad for connecting to the next level of electronic device such as a printed circuit board (PCB).
FIG. 1 is a sectional view of a portion of a conventional flip-chip package structure. As shown in FIG. 1, the package includes a die 10 having an active surface 12. The active surface 12 of the die 10 has an array of pads 14 thereon. The package also includes a flip-chip package substrate 20 that comprises of a plurality of wiring layers 24 (such as 24a, 24b, 24c . . . ) and a plurality of insulation layers 26 (such as 26a, 26b, 26c). The wiring layers 24 and the insulation layers 26 are alternately stacked one over the other. A plurality of through plugs 36 inside the insulation layer 26 connects the respective wiring layers 24 electrically. In general, two types of plugs 36 are generally used, a via plug 36a and a plating through hole (PTH) 36b. These two types of plugs are fabricated according to dimensional requirements.
The uppermost wiring layer 24 (the one closest to the uppermost surface 21 of the substrate 20) is a first wiring layer 24a. The first wiring layer 24a has a plurality of bump pads 30. Each bump pad 30 corresponds in position to a die pad 14 so that the die pad 14 and the bump pad 30 on the substrate 20 are electrically connected through a bump 16. Ultimately, through the wiring layers 24 and plugs 36, a portion of the die pads 14 on the die 10 fans out to areas underneath the active surface 12. The substrate 20 further includes a patterned solder mask 28 over the first insulation layer 26a and the first wiring layer 24a while exposing the plurality of bump pads 30 on the first wiring layer 24a. The solder mask 28 protects the first wiring layer 24a and the first insulation layer 26a. In addition, the bottom surface 22 of the substrate 20 has a plurality of ball pads 34 for connecting with the next level of electronic device through an electrical structure such as a solder ball (not shown).
FIG. 2A is a top view of the die in FIG. 1. The active surface 112 of the die 110 has a plurality of die pads 114 (such as 114a, 114b, 114c, 114d, . . . ) configured as an area array. According to their respective functions, the die pads 114 are divided into signal pads 114a, power pads 114b, ground pads 114c and core power/ground pads 114d. The signal pads 114a, the power pads 114b and the ground pads 114c surround the core power/ground pads 114d. Note that the signal pads 114a, the power pads 114b and the ground pads 114c are randomly distributed over the active surface 112 of the die 110 by convention. Hence, when the original die pads (not shown) on the die 110 is re-distributed to the active surface 112 of the die pad through a re-distribution layer (RDL), overall path length to the re-distributed die pad 114 will increase. Since signal transmission pathway is increased, electrical performance of the die 110 is compromised.
FIG. 2B is a top view of a portion of a flip-chip package substrate that corresponds to the die in FIG. 2A. As shown in FIG. 2B, the upper surface 121 of the flip-chip package substrate 120 has a plurality of bump pads 130 thereon (such as 130a, 130b, 130c, 130d, . . . ). All bump pads 130 are formed inside the die area 140 of the flip-chip package substrate 120 and positioned into an area array so that each bump pad 130 lies over a die pads 114 as shown in FIG. 2A. To link up with the signal pads 114a, the power pads 114b, ground pads 114c and core power/ground pads 114d on the die 110, the bump pads 130 on the substrate 120 may be similarly divided into signal bump pads 130a, power bump pads 130b, ground bump pads 130c and core power/ground bump pads 130d. The signal bump pads 130a, the power bump pads 130b and the ground bump pads 130c surround the core power/ground bump pads. Note that the signal pads 114a, the power pads 114b and the ground pads 114c are randomly distributed over the active surface 112 of the die 110 by convention. Hence, the signal bump pads 130a, the power bump pads 130b and the ground bump pads 130c are also randomly distributed over the upper surface 121 of the substrate 120.